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21–2
Table 21–1. External RAM Block Inputs and Outputs
Chapter 21: Simulation Library
Signal
ReadWaitRequest
ReadDataValid
Direction
Output
Output
Description
Stalls the interface when the Avalon-MM interface cannot respond immediately to a
read request.
Marks the rising clock edge when ReadData is asserted. Indicates that valid data is
present on the ReadData lines.
Table 21–2 shows the External RAM block parameters.
Table 21–2. External RAM Block Parameters
Name
Data Width
Address Width
Wait States Per Write
Maximum Latency
Size
Offset
Value
8, 16, 32, 64,
or 128
1–32
0–10
1–255
1–2 n (1)
1–2 n (1)
Description
Specifies the number of bits for the data. No other values are supported. 64 and
128 bit data widths require a Simulink fixed-point license.
Specifies the number of bits n for the address.
Specifies a fixed number of wait states for each write transfer.
Specifies the latency for pipelined read transfers.
Specifies the total size of the RAM in bytes (the number of addresses when you
use a range of addresses).
Specifies an offset for the RAM start address (the start address when you use a
range of addresses.
Notes to Table 21–2
(1) The size added to the offset must be less than 2 n where n is the address width.
Figure 21–1 shows an design example with the External RAM block.
Figure 21–1. External RAM Block Example
Multiple Port External RAM
The Multiple Port External RAM block is a simulation model of a multiple port
external RAM block. It stores and retrieves data from a range of addresses and is
compatible with the Avalon-MM interface.
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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